International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Design of a Power-Efficient Routing-Based Approximate Multiplier Using Parallel Prefix Adder and Compressor |
|---|---|
| ABSTRACT | Approximate computing has become an effective design methodology in order to develop high performance and energy-efficient digital signal processing (DSP) architectures as the issue of slight error in accuracy is no longer a concern. Of many components in DSP, the multiplier plays a significant role, as it has a direct contribution in regard to the power consumption, delay, and performance of the system. The paper proposes four energy-efficient Rounding-Based Approximate (RBA) multiplier architectures. The proposed architectures are able to approximate the input operands by rounding each to the closest power-of-two, such that the multiplication is performed using adding and shifting, instead of partial product generation and accumulation. Rounding the inputs leads to a less complex circuit overall, faster computing, and lower power dissipation. In addition to the four energy-efficient RBA multiplier architectures, one of the proposed architectures is a Reconfigurable Rounding-Based Approximate (RoBA) multiplier architecture that can increase the adaptability of both accuracy and energy efficiency, using a control signal. The proposed architectures were implemented and simulated in Verilog HDL utilizing Xilinx ISE 14.7 tools. Simulation results demonstrate that the proposed RBA and RoBA multipliers provide significant savings in power consumption and propagation delay in comparison to conventional multipliers, while still providing acceptable accuracy that is suitable for error-tolerant applications. |
| AUTHOR | J. SUSAN JENOVA, P.ARIVAZHAGAN PG Student, Dept. of ECE. Sir Issac Newton College of Engineering and Technology, Nagapattinam, TamilNadu, India Assistant Professor, Dept. of ECE, Sir Issac Newton College of Engineering and Technology, Nagapattinam TamilNadu, India |
| VOLUME | 180 |
| DOI | DOI: 10.15680/IJIRCCE.2026.1401088 |
| pdf/88_Design of a Power-Efficient Routing-Based Approximate Multiplier Using Parallel Prefix Adder and Compressor.pdf | |
| KEYWORDS | |
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