International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Low Power Meets High Performance: An Approximate MAC Architecture Using RoBA Multipliers and Adders |
|---|---|
| ABSTRACT | Multiply–accumulate (MAC) units are key components in digital signal processing and machine learning hardware, where power consumption and performance are critical design concerns. This paper proposes a low-power, high-performance approximate MAC architecture using rounding-based approximate (RoBA) multipliers and carry look-ahead (CLA) adders. The RoBA multiplier reduces complexity by approximating partial product generation and accumulation through rounding, while the CLA adder accelerates addition by minimizing carry propagation delay. By jointly applying approximation and fast addition techniques, the proposed MAC significantly lowers switching activity, area, and power consumption. The architecture is evaluated against an exact MAC using error metrics and hardware parameters. Results indicate substantial gains in energy efficiency and speed with only minor degradation in computational accuracy, making the proposed design well suited for error-tolerant applications such as multimedia processing and neural network acceleration. |
| AUTHOR | PROF. DR. SHILPA K C, NAGARAJ SAJJAN, NINGANNAGOUDA, PRAJWAL Department of Electronics Communication and Engineering, Dr. Ambedkar Institute of Technology, Bengaluru, India |
| VOLUME | 177 |
| DOI | DOI: 10.15680/IJIRCCE.2025.1312066 |
| pdf/66_Low Power Meets High Performance An Approximate MAC Architecture Using RoBA Multipliers and Adders.pdf | |
| KEYWORDS | |
| References | [1]. M. Hashemi and S. M. Fakhraie, "Energy-Efficient Approximate Multipliers for Deep Learning Accelerators, " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 3, pp. 542-555, Mar. 2021. [2]. R. Das, S. Dey and A. Mukherjee, "Low-Power Approximate MAC Using Truncation and Error Compensation, " in Proceedings of the 33rd International Conference on VLSI Design and 19th Embedded Systems Conference (VLSID), Bangalore, India, Jan. 2020, pp. 124-129. [3]. P. K. Meher and B. Adhikari, "Power-Efficient Approximate MAC Unit for Image Processing Applications, " IEEE Access, vol. 9, pp. 11123-11131, 2021. [4]. H. Kaur and M. S. Yadav, "A Review on Recent Approximate Adders for Low Power and Error-Resilient Applications, " Microelectronics Journal, vol. 112, pp. 105014, Jun. 2021. [5]. T. Ramesh and A. Srinivas, "Design of High-Speed Approximate MAC Unit Using RoBA Adders, " in International Journal of VLSI Design & Communication Systems (VLSICS), vol.13, no. 4, pp. 23-31, 202. |