International Journal of Innovative Research in Computer and Communication Engineering

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TITLE Performance Analysis of NMOS Power-Gated Approximate Multiplier
ABSTRACT This paper describes the design of an approximate multiplier that uses NMOS-based power gating to achieve low power and high-performance operation. The proposed approach integrates NMOS sleep transistors into XOR gate structures to minimize leakage power and reduce unnecessary switching activity during idle conditions. Approximation is mainly applied to the lower significant bits (LSBs), while the higher significant bits (MSBs) are maintained to ensure reliable output behaviour. This method lowers circuit complexity and enhances speed while keeping the critical portion of the result unaffected. The design is implemented using the Tanner EDA tool with 90 nm technology, and its performance is analysed in terms of power consumption, delay, and Power Delay Product (PDP). The results show that the proposed multiplier successfully reduces both dynamic and static power, making it suitable for low-power VLSI applications.
AUTHOR K. SRILAKSHMI, J. SAREESHA, K. VISHNU PRIYA, E. SWATHI, K. PAVAN SRI VASTAV Associate Professor, Department of Electronics and Communication Engineering, Seshadri Rao Gudlavalleru Engineering College, Gudlavalleru, Krishna, Andhra Pradesh, India Undergraduate Student, Department of Electronics and Communication Engineering, Seshadri Rao Gudlavalleru Engineering College, Gudlavalleru, Krishna, Andhra Pradesh, India
VOLUME 183
DOI DOI: 10.15680/IJIRCCE.2026.1404080
PDF pdf/80_Performance Analysis of NMOS Power-Gated Approximate Multiplier.pdf
KEYWORDS
References [1] Fang-Yigu, Ing-Chaolin and Jia-Wel Lin”, A Low-Power and High-Acuuracy Approximate Multiplier With Reconfigurable Truncation, IEEE, May 30 2022.
[2] Faranaz Sabetzadeh, Mohammad Hossein Moaiyeri”, An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications, IEEE, Feb 2023.
[3] Ayushi Vinodia”, Energy-Efficient Approximate Multiplier with Flexible Precision, IJRASET, May 2024.
[4] M. de la Guia Solaz, W. Han, and R. Conway, ‘‘A flexible low power DSP with a programmable truncated multiplier,’’ IEEE Trans. Circuits Syst., vol. 59, no. 11, pp. 2555–2568, Nov. 2012.
[5] R. Zendegani, M. Kamal, M. Bahadori, A. Afzali-Kusha, and M. Pedram, ‘‘RoBa multiplier: A rounding-based approximate multiplier for high speed yet energy-efficient digital signal processing,’’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 2, pp. 393–401, Feb. 2017.
[6] C. S. Wallace, ‘‘A suggestion for a fast multiplier,’’ IEEE Trans. Electron. Comput., vol. EC-13, no. 1, pp. 14–17, Feb. 1964.
[7] A. Weinberger, ‘‘4:2 carry-save adder module,’’ IBM Tech.
Discl. Bull., vol. 23, no. 8, pp. 3811–3814, 1981.
[8] A. Momeni, J. Han, P. Montuschi, and F. Lombardi, ‘‘Design and analysis of approximate compressors for multiplication,’’ IEEE Trans. Comput., vol. 64, no. 4, pp. 984–994, Apr. 2015.
[9] Z. Yang, J. Han, and F. Lombardi, ‘‘Approximate compressors for error resilient multiplier design,’’ in Proc. IEEE Int. Symp. Defect Fault Toler ance VLSI Nanotechnol. Syst. (DFTS), Oct. 2015, pp. 183–186.
[10] C.-H. Lin and I.-C. Lin, ‘‘High accuracy approximate multiplier with error correction,’’ in Proc. IEEE 31st Int. Conf. Comput. Design (ICCD), Oct. 2013, pp. 33–38.
[11] P.J.Edavoor,S.Raveendran,andA.D.Rahulkar,‘‘Approximatem ultiplier design using novel dual-stage 4:2 compressors,’’
IEEE Access, vol. 8, pp. 48337–48351, 2020
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