International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Performance-Optimized VLSI Architecture for Post-Quantum Cryptography Using SHA-3 |
|---|---|
| ABSTRACT | The rise of quantum computing threatens classical cryptographic systems, making the development of efficient post-quantum cryptography (PQC) hardware essential. Since the SHA-3 hash function is a key component in many PQC schemes, this paper proposes a performance-optimized VLSI architecture for SHA-3 designed to improve speed and reduce hardware resource usage. The architecture optimizes the Keccak permutation rounds through pipelining and efficient resource sharing, minimizing critical path delay while maintaining low area and power consumption. Implemented and synthesized on FPGA/ASIC platforms, the proposed design achieves higher throughput and improved efficiency compared to existing SHA-3 implementations, offering a practical hardware solution for securing post-quantum cryptographic systems. |
| AUTHOR | GAURAV KUMAR, DR. BHARTI CHOURASIA, DR. PRIYANKA JAISWAL M. Tech Scholar, Department of ECE, Sarvepalli Radhakrishnan University, Bhopal, India Professor and HOD, Department of ECE, Sarvepalli Radhakrishnan University, Bhopal, India Professor, Department of ECE, Sarvepalli Radhakrishnan University, Bhopal, India |
| VOLUME | 187 |
| DOI | DOI: 10.15680/IJIRCCE.2026.1408017 |
| pdf/17_Performance-Optimized VLSI Architecture for Post-Quantum Cryptography Using SHA-3.pdf | |
| KEYWORDS | |
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